IBM Research Demonstrates Path for Extending Current Chip-Making Technique

Risky Alternatives Could Be Postponed if Current Methods Can Be Modified to Last Longer

SAN JOSE, CA — (MARKET WIRE) — 02/20/2006 — IBM researchers today announced they have found a way to extend a key chip-manufacturing process to generate smaller chip circuits, potentially postponing the semiconductor industry’s high-risk conversion to an extremely expensive alternative.

IBM scientists have created the smallest, high-quality line patterns ever made using deep-ultraviolet (DUV, 193-nanometer) optical lithography — a technology currently used to essentially “print” circuits on chips. The distinct and uniformly spaced ridges are only 29.9 nanometers wide (a nanometer is a billionth of a meter). This is less than one-third the size of the 90-nanometer features now in mass production and below the 32 nanometers that industry consensus held as the limit for optical lithography techniques.

For decades, the semiconductor industry has relied on continually shrinking circuits to drive increases in the performance and function of chips and the products that use them. But as chip features now approach the fundamental scale limits of individual atoms and molecules, the future of this trend of relentless improvement, known as Moore’s Law, is being threatened. IBM’s new result indicates that a “high-index immersion” variant of DUV lithography may provide a path for extending Moore’s Law further, thus buying the industry time.

“Our goal is to push optical lithography as far as we can so the industry does not have to move to any expensive alternatives until absolutely necessary,” said Dr. Robert D. Allen, manager of lithography materials at IBM’s Almaden Research Center. “This result is the strongest evidence to date that the industry may have at least seven years of breathing room before any radical changes in chip-making techniques would be needed.”

The record-small pattern of well-defined and equally spaced 29.9-nanometer lines and spaces was created on a lithography test apparatus designed and built at IBM Almaden, using new materials developed by its collaborator, JSR Micro (Sunnyvale, California). The first technical details will be presented this week (Monday, Feb 20, 2006) at the SPIE Microlithography 2006 conference being held in San Jose, California.

“We believe that high-index liquid imaging will enable the extension of today’s optical lithography through the 45- and 32-nanometer technology nodes,” said Mark Slezak, technical manager of JSR Micro, Inc. “Our industry faces tough questions about which lithography technology will allow us to be successful below 32 nanometers. This new result gives us another data point favoring the continuation of optical immersion lithography.”