Newport, Isle of Wight, UK – 20 May 2009 – RF Engines Limited (RFEL), the specialists in high performance signal processing design work, have been contracted by SELEX Galileo to develop a new algorithm and the optimum architecture for determining the fine time of arrival of certain classified signals. The design will also be implemented [...]
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Parser Used as Building Block for Speedster FPGA Development Software
Verific Design Automation today announced that Achronix Semiconductor Corporation, developer of the world’s fastest field programmable gate array (FPGA) called Speedster, uses Verific’s Netlist-Only Parser in its Achronix CAD Environment (ACE).
Verific is best known for its Verilog, SystemVerilog and VHDL hardware description level (HDL) [...]
Company leverages patented picoPIPE™ acceleration technology to deliver the world’s fastest FPGA, capable of 1.5 GHz peak performance.
First device in the Speedster™ family embeds 20 lanes of 10.3 Gbps SerDes and four independent 1066 Mbps DDR2/DDR3 controllers.
Speedster uses familiar LUT-based fabric and standard synthesis and simulation tools so designers can use their existing RTL.
Signaling [...]
Avnet MicroBlaze Processor Linux DVD, Kit and Linux for MicroBlaze Processor SpeedWay Design Workshop Series Offers Complete Design and Support Solution for Embedded Processor Applications
Embedded Systems Conference Silicon Valley 2008
The Avnet Electronics Marketing Americas business region of Avnet, Inc. (NYSE:AVT), announces the release of a new Xilinx® MicroBlaze® Processor Linux DVD, MicroBlaze Processor Linux Starter [...]
