Parser Used as Building Block for Speedster FPGA Development Software
Verific Design Automation today announced that Achronix Semiconductor Corporation, developer of the world’s fastest field programmable gate array (FPGA) called Speedster, uses Verific’s Netlist-Only Parser in its Achronix CAD Environment (ACE).
Verific is best known for its Verilog, SystemVerilog and VHDL hardware description level (HDL) [...]

May 29 Tutorial to Highlight Ways to Rapidly Find, Isolate Bugs
Carbon Design Systems
Who: Carbon Design Systems™, the leading supplier of tools for the automatic creation, validation and deployment of virtual hardware models
What: Will host a webinar for software developers, hardware architects and firmware designers on accelerating system validation.
Replay is a system-level [...]